In the electronic arts it is often desired to perform data exchange between different devices. These data can be information to be processed further by the receiving device or control signals controlling the receiving device. The several devices are connected by a bus which allows data transfer from one sending device to typically one receiving device at a time. Master devices are authorized to demand bus access in order to initiate such a data transfer, slave devices can not initiate a transfer. Several masters can demand bus access simultaneously and arbitrate for the bus. An arbiter grants the bus to the master who wins the arbitration.
In typical bus systems, at least one slave is a memory. A memory often needs to reply in an indivisible access to one or more subsequent bus transactions with the same bus master. Such bus transactions are called "atomic" and include "read after write" or "write after read". Here, "read after write" includes several successive reads followed by a final write and "write after read" includes several successive writes followed by a final read. Some buses support atomicity, e.g. the VME bus has a special signal line to "lock" the bus for atomic transactions and prevent access by other masters. But in these cases the bus including the protocol must be constructed to allow atomic transactions.
Write after read as well as read after write transactions are necessary in a Content Associative Memory (CAM). It is desirable to connect CAM to an existing system without having to modify the bus or the bus protocol.
There is a need for making atomic transactions possible on a bus without changing the bus width or the bus protocol.